Control modules and circuits



June l5, 1965 Filed Oct. 9. 1961 y Counter P. M; KINTNER 3,189,755CONTROL MODULES AND CIRCUITS 15 Sheets-Sheet 1 INVENTOR Paul M. KnfnerATTORNEYS June 15, 1965 Filed Oct. 9, 1961 P. M. KlNfrNaR 3,189,755

CONTROL MODULES AND CIRCUITS 1:5 sheets-shim 2 INVENTORY Paul M.KinfnerBY ATTORNEYS P. M. KINTNER CONTROL MODULES AND CIRCUITS June 15, 1965 13Sheets-Sheet 3 Filed Oct. 9. 1961 EEIAII .AIIrl w25@ @2m Eo Ill XNVENTORBY Paul M.Kin'rne'r @maw nwhg ATTORNEYS June l5, 1965 P. M. KINTNERCONTROL MODULES AND CIRCUITS 13 sheets-sheet 4 Filed Oct. 9. 1961 FIG.3c

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CONTROL MODULES AND CIRCUITS 13 Sheets-Sheet 13 Filed Oct. 9. 1951ATTORNEYS United States Patent O 3,1t,755 CGNTRL MODULES AND CIRCUTSPaul M. Kintner, Huntington Station, NY., assigner to Cutler-Hammer,Inc., Milwaukee, Wis., a corporation of Delaware Filed Uct. 9, 1961,Ser. No. 143,925 16 Claims. (Cl. 367-885) This invention relates tocontrol modules, and to control circuits formed thereof.

Many control circuits are used in industry at the present time tocontrol machines, computer readout, data processing, etc. Althoughindividualized control circuits may be designed to meet the requirementsof each application, and an individual unit constructed, in general thisrequires considerable development time and entails a considerablemanufacturing expense.

It is a primary object of the present invention to provide a series ofdigital control modules which may be interconnected to meet therequirements of many different types of control applications. By the useof modules, which may be standardized for quantity production, much ofthe design and manufacturing expense of an individual installation isavoided.

The modular system in accordance with the invention is based on theconcept that most control actions may be separated into a series ofsteps to be performed in succession. At each step one or more controloperations may be actuated. The control operation may usually beeffected by a switching action, such as closing a relay, starting amotor, gating or shifting a register, incrementing a counter, etc.

A simple series of sequential steps, with control instrumentation ateach step, may result in an unduly elaborate system in situations wheretwo or more steps are repeated in obtaining the overall control.Further, the overall operation may involve conditional factors where atsome point in the control the subsequent step sequence depends on theeffect previously obtained.

Part of the concept is therefore to provide a modular system wherein anydesired step sequence can be obtained, including repeating a certainstep or steps and jumping to steps out of normal sequence, so that therequirements of any particular application can be met. The repeating orjump actions may be predetermined to occur at desired points in thecontrol cycle, or made conditional on the accomplishment of a particularresult, etc.

In a given application some steps may be performed very rapidly, whileothers may require a longer time. For example, when electronic devicesare to be switched from one condition to another at given steps, theswitching may be capable of being performed very quickly. However, whena mechanical device such as a relay must be actuated, or a mechanicalelement moved, more time may be required. Further, in many industrialapplications a series of control steps may be performed, and then it maybe necessary to await the outcome of that series of steps beforeperforming additional steps.

ln the modular system of the present invention basic Timer and Steppermodules are provided for performing a sequence of steps in regular orderat a desired speed. The time allowed for each step before proceeding tothe next may be selected as desired.

In order to allow steps to be repeated, or to be performed out of theregular progressive step sequence, a Jump module is provided which isoperable at any desired step to jump to another step. The jump may be toeither a succeeding or preceding step. ln the latter case, a series ofsteps will be repeated until the jump is inhibited to allow stepping toproceed. The inhibition lCe may be effected after a desired number ofjumps, or made conditional upon some other action taking place, etc.

A Delay module is provided which can delay the progressive `stepping atany desired step, so as to allow time for the completion of thecorresponding control function before proceeding to the next step. Thedelay is usually a iixed time delay which is selected as desired.

A Wait module is provided which is actuable at any desired step so as tostop operation until a Go Ahead signal is received.

In general, the delay, wait and jump actions are controlled by thestepper unit so as to perform the respective action at the desired step.The jump unit then functions to change the stepper to a preceding or asubsequent step as required. The delay and wait units perform theircorresponding functions by stopping the timer for the desired intervals.

In passing through a series of steps, whether in normal step sequence orin a sequence involving jumps, there are transition periods betweensteps which, although short, may result in improper functioning.Accordingly, the timer is arranged to deliver clock pulses which liebetween the stepping pulses, and these clock pulses are used as requiredto insure proper operation of the various units. They are commonlyapplied to jump, delay and wait modular units in order to allowsufficient time for a step to take place before the control of the unitby that step is effective.

The timer is arranged for manual stepping, if desired, so that astep-by-step advance can be effected for checkout and maintenancepurposes.

Some kinds of control may not require all the actions described above.In such case, the modules corresponding to the unneeded actions need notbe employed. Also, some types of control may require actions in additionto those described, in which case individual circuits may be designedfor that particular application, or additional modules developed if theneed warrants.

In the modules themselves, transistor and semiconductor diode circuitsare employed for reliability, low power consumption, and generalconvenience of use. Particular features have been introduced in thevarious modules which are believed advantageous. However, in the broaderaspects of the invention many modifications in individual modular unitsare possible.

The invention will be explained in conjunction with specific embodimentsthereof, including specific modular units and control circuits employingthe modular units.

In the drawings:

FIG. l is a step diagram illustrating a modular arrangement forperforming certain operations in a particular sequence;

FIG. 2 shows module units interconnected to perform the step sequence ofFIG. l;

FIGS. 3, 3a, 3b and 3c show a circuit diagram, symbol and waveforms of aTimer module;

FIGS. 4, 4a and 4b show a circuit diagram, symbol and waveforms of aStepper module;

FIG. 5 shows the interconnection of two stepper modules to give agreater number of steps;

FIGS. 6, 6a and 6b show a circuit diagram, symbol and waveforms of a Iump modular unit;

FIGS. 7, 7a and 7b are similar illustrations for a Delay modular unit;

FIGS. 8, 8a and 8b are similar illustrations for a Wait modular unit;and

FIGS. 9 and 10 illustrate different arrangements of the modular units toperform different control functions.

Referring now to FIG. 1, a step diagram is shown for performing fourcontrol operations in sequence, with a repetition of operations 1 and 2prior to proceeding with operation 3.

disagree Five blocks are shown with the numerals to 4 in the upperleft-hand corners to indicate the step numbers. The timer is not shownexplicitly, but is assumed to control a stepper giving step outputsperforming the indicated functions.

At the 0 step it is desired to wait until a go-ahead signal is received,as indicated. The go-ahead signal may be produced manually orautomatically depending upon the application. At step 1, operation 1 isperformed, which may be any type of control desired. At step 2,operition 2 is performed. It is then desired to repeat operations 1 and2, and accordingly a jump unit is actuated at step 2 so that, afteroperation 2 has been performed, the control unit steps back tooperation 1. This is indicated by connection 1I from the jump portion ofstep 2 back to step l. This repeat action may be terminated by aninhibiting signal applied through line 12 to the jump unit. In thisembodiment it is assumed that the repeat is to be terminated after aselected number of jumps. Accordingly, a counter 13 is provided to countthe number of jumps, and the inhibiting signal is applied to line 1 2after the desired number of repeats has been performed. In otherembodiments it may be desired to repeat the jump until a desired resulthas been obtained and a corresponding signal then produced to inhibitfurther jumps.

After the jump is inhibited, the control unit proceeds to step 3 andoperation 3 is performed. It is assumed that a time exceeding the normalinterval between steps is required for operation 3, and accordingly adelay is produced as indicated. After the delay, the system steps tostep 4 and operation 4 is performed.

It is then assumed that the control system is to return to its initialcondition, ready for another control operation. Accordingly, the systemsteps back to the 0 step. as indicated by line 14.

Referring to FIG. 2, interconnections between timer, stepper, wait, jumpand delay units are shown for effecting the control operation depictedin FIG. 1. The symbols for the several units are shown hereinafter inconnection with the circuit diagrams, and the detailed manner in whichthese circuits function will be understood therefrom. For the moment, itsuffices to point out the overall functioning of the control circuit.

Stepping pulses are applied from Timer 15 through line f i6 to Stepper17 to cause the latter to make one step for each step pulse. Steps 0through 4 give outputs at terminals T, P, K, E, C, in succession. Noexternal operation is required to be performed at step 0, this stepbeing used at a rest step awaiting initial action. For the remainingsteps, outputs are shown indicating the corresponding operations. Theseoutputs are in the form of voltage (or current) pulses which may rbeutilized to perform the required operations. If the operations areelectronic, as'by electronic switches, gates, etc., the voltages may beutilized directly to elfect the necessary control. Or, they may besupplied to switches, relays, etc., as appropriate for the desiredoperations.

At step 0 it is desired to wait until a go-ahead signal is received.Accordingly, the T output is supplied through line 18 to Wait unit 19.Clock pulses are also supplied from timer 15 through line 21 to the Waitunit, and upon the occurrence of the clock pulse an inhibit signal issupplied through line 22 which stops the operation of timer l5. Thiscontinues until a go-ahead signal is supplied through line 23 to theWait unit, terminating the inhibiting signal in line 22. The timerthereupon resumes operation and the stepper 17 moves to step 1, yieldingan output from P to perform operation 1.

The next step pulse moves stepper 1.7 to step 2, giving an output at Kto perform operation 2. The output is also supplied through line 24 tothe Jump unit 25. This unit is also supplied with clock pulses from line21., and upon the occurrence of the clock pulse a signal is suppliedfrom output K through line 26 to stepper input N, corresponding tostep 1. Accordingly the stepper is stepped back to step l as required bythe diagram of FIG. 1. Actually, as will appear from the descriptiongiven hereafter, in setting a new step into the stepper unit, thecondition thereof is iirst cleared and then changed to the desired step.The clear signal is supplied from jump output E through line 27 tostepper input M, and the signal in line 26 then sets the stepper to step1.

Output C of jump unit 25 gives a pulse for each jump, and these aresupplied through line 2S to counter 13. When the counter has counted thenecessary number of jumps, an inhibiting signal is supplied through line12 to jump input B. Accordingly, the jump is discontinued and thestepper moves to step 3 when the next step'pulse is received from lineI6.

At this step a signal `through line 32 is supplied to Delay unit 33.Upon the occurrence of a clock pulse through line 21;, an inhibitingsignal is supplie-:l from Delay 33 through line 34 to timer input L, andstops the action of the timer. The delay unit is designed to provide afixed delay whose duration may bek selected as required, and upontermination of this delay the timer resumes operation to cause stepper17 to move to step 4.

This completes the series of operations illustrated in FIG. 1, and theoperation is to return to step 0, ready for another gol-ahead signal. Ajump unit could be used to jump from step 4 to step 0. However, in theembodiment described the stepper 17 is designed to give steps (l through4 and a connection from `stepper output F to input U through line 35causes the stepper to return to the 0 step, whereupon the Wait unit isactuated by a puls-e through line 1S and the initial condition isobtained.

FIG. 3 is a circuit diagram of a timer module. From the symbol shown inFIG. 3a', it will be seen that the timer functionsy to generate astepperL signal at output T and a clock signal at output P. A number ofinhibiting input circuits are supplied, lettered M, L, etc., asindicated. Also, a single step input can be applied at R which inhibitsthe automatic generation of the stepping and clock signals, and allowsthe timer to be stepped from one step to the next manually. This isuseful for checkout and maintenance purposes.

FIG. 3b illustrates the stepping and clock sequence. The time from line36 to line 37 is designated the step period. This may be selected asdesired for a required fundamental or free-running speed of operation.It is here assumed to be 200 microseconds corresponding to a basic speedof operation of 5,000 steps per second. Numerical values will often begiven hereinafter to facilitate understanding, but it will be understoodthat the values may be changed as required to meet the conditions of theparticular application.

The stepper signal consists of relatively short negative pulses 3S whichrecur at the step interval period. As shown, there is a delay 39 fromthe beginning of a step period to the step pulse which insures that theclock pulse has gone off throughout the whole system before the step ismade. After an additional delay to insure that the new step value hasstabilized throughout the system, the clock pulse 4d is initiated. Thisis a positive-going pulse terminating at the end of the step period. Inthe circuits described hereinafter, switching is from a negative voltageto ground and vice versa. However, the magnitude and polarity of thesignals may be selected to conform to the detailed circuit design.

Referring now to FIG. 3, the timer module board is shown by the dashed-box 42. Clock and stepper outputs are produced at output terminals PandT, a plurality of input inhibiting circuits B, C L, M are provided, anda single step input R. Terminals A and V are `for connection to thepower supply. PNP transistors are used in this embodiment, as indicatedby the direction of the emitter arrows. Normally A is grounded asindicated in dotted lines, and V is connected to a minus voltage, forexample l0 volts. This will be assumed hereinafter for convenience ofexplanation. However, if desired A could be.

connected to the plus side of the power supply, and the minus sideconnected to V and grounded, etc., as will be understood by those in theart.

Transistors Q4 and Q5 are connected as a multivibrator which, acting asan oscillator, generates the basic timing signals. yQ3 acts as a switchwhich, if open, will stop the multivibrator. Q1 is an inverter whichaccepts the inhibit inputs and generates the control signal for Q3. Q6and Q7 form a two-stage amplier for the clock signal. QS and Q9 arepulse generators forming the stepper pulse output. Q2 is a pulsegenerator accepting, say, a contact closure from a grounded switch, asshown, and the output thereof is applied to Q3 to turn that transistoron for the duration of a single step cycle.

The basic waveforms for the timer circuit of FIG. 3 are shown in FIG.3c. Assume that Q3 is oi (nonconducting), and goes on (conducting) atthe beginning of a step period. The collector of Q3 will then changefrom a negative potential to ground as shown by waveform 45. Previous toQ3 going on, the path from the emitter of Q4 to ground will be open, nocurrent can flow through Q4, and the Q4 collector will be negative,since it is connected to V through load resistor 46. 0n the other hand,Q5 will be on through the base current supplied by resistor 47, and thecollector of Q5 will be at substantially ground potential since theemitter is connected to A.

A ground return will be supplied to Q4 when Q3 is turned on, and thecollector of Q4 will be driven to ground by the control current suppliedthrough resistor 48 to the base. A positive-going transient will becoupled through capacitor 49 to the base of Q5, turning Q5 olf andstarting astable multivibrator action. The collector of QS will gonegative to a point limited substantially by the load represented byresistor 5I and resistor 52. However, there will be no loading ofcapacitor 53 because the diode 54 will furnish a disconnect action.

At the instant of disconnect, the current through resistor 55,previously going through diode 54 and Q5, will be coupled throughcapacitor 53 to the base of Q4, reinforcing the current from resistor4S. After a period of time T1, shown in FIG. 3c, capacitor 49 willcharge sutiiciently so that a positive voltage will no longer be appliedto the base of Q5, and Q5 will be turned on again by the current throughresistor 47. The collector of Q5 will be driven to ground, and in theprocess will pick up the junction 56 through diode 54. A positivetransient will be coupled through capacitor 53 to Q4, turning Q4 of. Thecollector of Q4 will go negative, coupling a negative transient throughcapacitor 49 to the base of Q5.

After a period of time T2, the positive transient coupled throughcapacitor 53 will decay until the base of Q4 is no longer positive. Q4will then be turned on again, and the cycle of action repeated.

The Q5 collector signal is sent through two stages Q6 and Q7 whichfunction as inverting amplifiers. Capacitor 57 is included in thecoupling between the stages in order to give a short rise time for theoutput signal, from the Q7 collector. The waveforms given in FIG. 3cillustrate the above-described operation, and it will be observed thatthe clock signal at the Q7 collector, and appearing at output terminalP, corresponds to that shown at 41 in FIG. 3b.

In order to produce the stepper signal in proper timed relationship tothe clock signal, the collector of Q6 is connected through line 59 andcapacitor 61 to the base of Q8. QS is a pulse generator which provides adelay T3 as shown by waveform 62 in FIG. 3c, before the step pulse isgenerated by Q9. This delay allows time between the going oit o-f theclock signal and the production of the next stepping signal whichchanges the system to a new step. This allowance is desirable becausethe clock signal may be transmitted throughout the system by means oflogic units or amplifiers, and delays will com- Y monly be encounteredin these units.

Describing the pulse generator action of QS, the base of Q8 is connectedthrough resistor 63 to -V. When the collector output of Q6 in line 59goes positive at the beginning of T1, a positive voltage will be appliedto the base of Q8, Q8 will be cut off, and its collector will gonegative. Capacitor 61 will then charge through resistor 63 toward thenegative potential of -V, and after an interval determined by thecircuit time constant, the base of Q3 will go negative and turn QS on.This terminates the pulse at the Q8 collector as indicated at 62' inwaveform 62.

The positive-going trailing edge of pulse 62,' will initiate a negativepulse at the collector output of Q9. This will persist until capacitor64 charges through resistor 65 to the point where the Ibase of Q9 goesnegative and turns Q9 on. Accordingly, an output step signal at terminalT will be produced, as indicated at 38 of waveform 66. This is thestepper signal of FIG. 3b.

Describing now the inhibiting action, in the absence of inhibitingsignals the potentials at the inhibiting inputs B, C L, M will be atground. When a negative voltage is applied to any one of these inputs,the base of Q1 will go negative, turning QI on and bringing itscollector to substantially ground. The collector of Q1 is connected tothe base of Q3 through a voltage divider composed of resistors 67 and68. These are selected so that when Q1 goes on, Q3 is turned otf, sincecurrent will no longer be supplied through resistor 67 to the base ofQ3. With Q3 off, the emitter of Q4 is disconnected from ground, sotlliat the multivibrator action described above connot take p ace.

When the inhibiting signal is removed, the base of QI will return -toground, Q1 will be turned off, Q3 turned on, and multivibrator actionstarted. In order to achieve a short rise time and assure the initiationof the multivibrator action, the collector of Q3 is coupled throughcapacitor 69 to the base of QI. This results in a trigger action andgives a steep wavefront at the collector of Q3, once Q3 moves past thethreshold of conduction. A lock-up action is supplied by the connectionthrough resistor 52 from the collector of Q5 to the base of Q3. Thisinsures that a clock cycle, once started, will be completed.

The single step action is produced by transistor Q2 connected as a pulsegenerator. Terminal R is normally held at -V through a high resistor 71,and capacitor 72 is charged. This charging results from the connectionthrough resistor 73 to the base of Q2, and the connection of the latterthrough 74 to -V. The base of Q2 will be negative and Q2 will be on, butthe negative potential of its base will be limited by base-emitter diodeaction, to say, m0.25 volt.

The input circuit to R may be normally open, as illustrated by the openswitch 75, or normally negative.

When terminal R is brought to ground, as by closing switch 75, apositive transient is coupled through capacitor 72 ,to the base of Q2,driving the base above ground and turning Q2 off. The Q2 collector willthen go negative and supply current to the base of Q3 through resistor76, turning Q3 on and starting the multivibrator action.

In the meantime capacitor 72 will discharge toward -V, and when the baseof Q2 goes negative to ground it is turned on. This brings the Q2collector to ground and turns off Q3 to stop the multivibrator. The timeconstant of discharge of capacitor 72 can be made sufciently short sothat Q2 remains olf for only a short time, usually an interval greaterthan T1 and less than T2 in FIG. 3c, so that Q3 can reopen at the end ofone cycle.

When the input to R is removed, as by opening switch 75, capacitor 72.is allowed to recharge, ready for the next stepping.

Resistor 73 reduces .the susceptibility of the circuit to falseoperation by input noise, since the noise must produce a current throughtheresistor sulicient to give an IR drop equal to the voltage requiredto turn Q2 ott.

When single-step action is desired, one of the inhibit inputs B, C L, Mis supplied with a permanent negative voltage so that the multivibratoraction is normally inhibited. This keeps Q3 normally open, with thepulse generated by Q2 overriding this inhibit for one cycle.

ln the module of FIG. 3, as well as subsequent modules describedhereinafter, .the terminals are preferably brought out to a single edgeof the module board, to facilitate connections thereto. However, in thedrawings herein they are brought out to several edges to avoid drawingcomplexity and promote ready understanding.

FIG. 4 is a circuit digrarn of the stepper module unit. As shown, i-tcomprises tive pairs of transistors, Q10- Qll, Q12-Q13 QMS-Q19, eachpair being connected as cross-coupled iip-iiops and the several pairsinterconnected to form a tive-stage counter. By connecting the outputback to the input, it will function as a ring counter. Or, two units maybe operated :in tandem to function as a decade ring counter, etc.

As seen in FIG. 4a, there are tive outputs 0, l, 2, 3, 4, correspondingto the five stages. There are also live set inputs whose function is toset the counter at any desired step. Normal step input signals areapplied to input H. A clear signal to input M functions with a given setinput to step the coun-ter to the desired. step.

In operation oneV and only one of the stages is in the l state at anygiven time, the other being in the state (except that when being clearedfor a jump action all stages are momentarily in the 0 state). It isassumed that a l output corresponds to an output at ground poten-tial,and that a 0 output is a negative voltage substantially equal to V.Considering the first stage including transistors Q and Q11, a "1 outputat T corresponds to Q10 on and Q11 oit. For a "0 output, Q10 would beott and Q11 on.

The stepper is advanced one step by changing the 1 ilip-ilop to 0 andcausing the next hip-dop to go from a 0 to a 1. The coupling action isobtained by transmitting a positive-going transient from the l stage tothe next through a capacitor-diode gate. One` such gate coupling the rststage to the second comprises capacitor 31, diode S2. and resistor 33.The several stages and diode gates are similar so that only selectedones will be described. The positive-going transient is derived from thesecond transistor in each stage, that being the transistor whosecollector goes to ground when the stage goes from a "1 t0 a 0.

With the iirst stage in the "1 condition, the potential of line S4 willbe negative since Q11 will be off. With the next stage in the 0 state,transistor Q13 will be on and the potential of line 85 will besubstantially ground. Capacitor S1 will then charge through resistor S3.

When the first stage is changed so the 0 condition, Q11 will be turnedon and bring .the potential of line 34 to substantially ground. Thuscapacitor 81 will deliver a positive transient through diode 82 to thebase of Q13, turning that transistor olf. VBy multivibrator actionbetween Q12 and Q13, Q12 will be turned on and produce a 1 output atterminal P.

This stepping action is initiated by a negative step pulse such as pulse38 in FIG. 4b, applied to input H. Diode 87 thereupon conducts andapplies a negative voltage to the bases of the second transistors ineach stage, that is, to Q11, Q13 Q19 through the respective resistors38.

The tirst stage, which was in a "1 condition with Q11 ott, will therebybe forced to the 0 condition, with Q11 on. Since the other stages arealready in the "0 condition, the negative step pulse will have noeffect.

However, when Q11 goes on, the aforesaid positive transient throughcapacitor 81 is in a direction to turn Q13 ott. The length of the steppulse is made sutliciently short, compared to .the duration of thetransient so that S the transient prevails and Q13 is turned oit.V Thisputs the second stage in the l state and delivers a l output at P.

it will therefore be seen that, upon the occurrence of a step pulse atH, whichever stage is a "1 will be changed to 0 and the next succeedingstage from 0 to 1.

When a jump action is to occur, all stages are momentarily cleared, thatis, set lto 0, and then the desire-d stage is setto 1.

This is :accomplished by supplying a clear pulse such as shown 4byWaveform 89 to input M. Diode 9:1 conducts and drives the bases of thevsecond transistors in each stage negative, thereby turning all stage tothe "0 condition. Since'one of the stages will previously have been inthe "1 state, the `duration of the clear pulse is made greater than theset 1 transient, so that the clear pulse prevails. A negative set pulsesuch as4 shown by wave- :tor-rn 92 is then` applied to one of theexternal set inputs S, N, etc. corresponding to the stage desired to beset to l. This negative set 'pulse 92 immediately follows the clearpulse, and is supplied to the base of the rst transistor in the selectedstage, thereby turning that transistor on, and yielding a l output atthe cor-responding output terminal T, P, etc.

It will be n oted that the capacitoradiode gate for stage 1 has itsinput'at terminal U, Also, the collector of the `second transistor 19 ofthe last stage is brought out to terminal F. By connecting F to U,continuous ring stepping can be obtained. Or, additional stepper modulesmay be connected so as to obtain a greater number of steps when desired.Y

lFIG. 5 illustra-tes the interconnections of two stepper modules to givean overall count lfrom 0 to 9. Als will lbe observed, terminal F of thefirst stepper is connected to U of the second, and F of the second isconnected back to U vof the rst. The step inputs H .are connectedtogether, an-d also the clear inputs M.

The .arrangement of F-IG. 5 will be recognized as a decade counter. Two`decade counters may be interconnected to give steps, by connecting step9 of the first decade counter to the step inputs H of the second decadecounter through a coupler unitv which advances the second decade counter`one step for each ten steps of the rst decade counter. The arrangementof decade counters to count :any number of digits in a decimal system isknown in the art and need not be described in detail.

FIGS. 6, 6a and 6b illustrate a jump modular unit. More than one jumpunit may be placed `on a given module board, but only one will bedescribed.

The jump unit responds to a given step number value and gene-rates theneces-sary signals to place a new step number into the stepper. Theclocksigna-l is employe-d to prevent the jump signals from beinggenerated until the lstep opera-tion has been completed following whichthe jump is .to takeV place. Also, provision is made to inhibit thegeneration of the jump signals so as to allow the stepper to advance tothe next step.

As seen from FIG. 6a, two inputs -D and H are provided to recognize thestep number.- With a continuous step sequence from 0 to 4 or` 0 to 9,only one input is required andthe other may be grounded. However, whentwo decades are .arranged to count from 0 to 99, two inputs are requiredin order to recognize the status of each decade counter. More inputscould be provided for counting larger numberot" steps, but 100 stepssuffices for most practical applications.V

Input F is for the clock signal Land input B for the inhibit signal. Twooutputs J and K are provided to step the stepper to the desired newstep. As in the case of the step number inputs, one output sulces for acontinuous step counter, but two lare provided for individual con-Vnection to two `decade counters arranged to count from 0 to 99.V OutputE provides the clear signal to the stepper. An output C is providedwhich can be connected -to a counter to count the number of jumps.

Referring to FlG. 6, Q21 is the inhibit stage. Q22 generates a Vsignal`when the correct step number for the jump tand the `clock signal arereceived. Q23 is a pulse generator for generating the clear pulse, andQ24 is a pulse generato-r for generating the set 1 pulse.

Step number and clock inputs D, H and F are connected through similarresistors 93 to the base of Q22. If any of these inputs is negative, Q22will be on and its collect-or will be at ground potential. iHowever,when all of the inputs are at ground Q22 will be turned off, causing theQ22 collector to go negative (assuming no inhibiting from Q21).Capacitor 94 will thereupon charge through the base of Q23 to -Vpotential. The collector of Q22 remains negative through the clockperiod shown at 41 in FIG. 6b and goes to ground at the end of theperiod due to the clock going ofi.

The positive-going transient at the collector of Q22 is transmittedthrough capacitor 94 to the base of" Q23, thereby turning Q23 `oii a-ndproducing a negative pulse through diode 95 to output E. The dur-ationof the transient is selected to produce an output pulse at E of theproper length for the `clear signal 89 as previously described.

The Q23 pulse generator is similar to the QS pulse generator in FIG. 3,except for circuit constants, and the detailed operation need not bedescribed again.

Since ythe Q23 collector is negative during the clear pulse interval,capacitor 96 wil-l charge during this interval and, upon termination ofthe clear pulse, a positive transient will 'be delivered to the base ofQ24. A second negative pulse will then be delivered by Q24 to outputs Iand K, corresponding to the set pulse 92 of FlG. 6b. The constantsassociated with pulse generator 24 are selected to give a set pulsewhich is substantially shorter than the clear purl-se.

In order to facilitate counting of jumps, the collector of Q22 is made`available at output C.

The inhibiting of the jump signal outputs is obtained by applying groundpotential to input B. Q21 will thereupon be turned ofi, and the negativecollector will apply `a negative potential through resistor 97 to thebase of Q22. This prevents Q22 from being turned oit by terminals D, Hand F all going to ground, thereby inhibiting the generation of theoutput pulses. The inhibit signal to B is applied before the beginningof the clock signal 41 in order to produce this inhibiting action.

IFGS. 7, 7a a-nd 7b illustrate the delay module unit. Several delayunits may be placed on a given module, but `only one is shown.

The delay unit responds to 'a given step number and generate-s a pulsewhich is applied to the timer unit (FIG. 3) in order to stop the timeroscillator for a fixed time period. The unit includes inputs D and E forrecognizing the step number at which the delay is to be introduced, .andinput F for the clock signal. The timer inhibit signal is from output C.

FIG. 7b shows a clock waveform 41 with a dotted pulse 33 correspondingto the step at which the delay is to be introduced. The delay is tostart at 9S and continue to 99. 98 corresponds to the beginning of theclock signal succeeding step pulse 38. Due to the interval therebetween,the stepper will have had time to perform its action, and step signalswill be present at inputs D and E at the time the clock signal isapplied to F. Two inputs D and E are provided for the step number asdescribed in connection with the jump unit. When all three inputs E, D,F are at ground potential, transistor Q25 wil-l be turned olf and itscollector will'be negative.

In this unit it is desired to inhibit the timer oscillator during thegeneration of the corresponding clock signal, so that a direct-coupledtransistor stage Q25 is provided for inversion. Consequently Q26 will beturned on and l@ -its collector will be at ground potential immediatelyfollowing the beginning ot the clock pulse.

Transistors Q26 and Q27 are connected in the manner described for Q22and Q23 of FIG. 6 so as to function as a pulse generator. However, sincethe desired delay may vary for dilerent applications, here an externalcapacitor 10i is employed so that its value can be selected to producethe required delay.

Transistor Q27 will be cut oif at the beginning of the delay time andturned on at the end of the time as determined by the value of capacitorlill, generating a delay signal as shown by waveform 1tl2. In effect,the clock pulse is stretched as shown at 106. The output at C may besupplied to any one of the timer inhibit inputs and will stop the timeroscillator as described before.

FIGS.. 8, 8a and 8b show the Wait unit. This unit responds to a givenstep number from the stepper at inputs B and E, as described for the Iump and Delay units, upon the occurrence ot a clock signal at input S.The output at C is a negative-going signal which may be supplied to oneof the inhibiting inputs of the timer to stop the timer oscillator.Provision is made for two types `olf Go-ahead signals, one of which is aD.C. signal at ground potential and the other a transient or A.C.signal. In the first, the D.C. ground potential will over-ride theinputs producing the inhibit action, and in the second a positive-goingtransient provides the over-riding action.

In many applications either type of Go-ahead signal may be used.However, where the signal may be produced in advance of the step atwhich the wait would ordinarily take place, the D.C. input willordinarily be used. Also, where the signal is of uncertain duration, aswhen produced manually, the A.C. input may be preferable to avoid thepossibility that the wait step will be reached again betere the Go-ahead-signal is removed.

Referring to FiG. 8, Q30 has its input connected through resistors toterminals B, E and S, and generates a negative inhibiting output at C,as shown by waveform 103, when the inputs are at ground potential. Thisfunctions in the manner described for Q22 of FIG. 6.

Q29 is in the D.C. Go-ahead stage. With the input circuit to F open (ornegative), a negative potential from l-V and resistor 104 will beapplied through resistor 105 to the base of Q29, thereby holding Q29 on.Accordingly, its collector will normally be substantially at groundpotential and will not inhibit the operation of Q30. However, when inputF is grounded, Q29 is turned oi and the negative potential of itscollector will drive the base of Q3@ negative, thereby turning on Q30and terminating the inhibit signal 163. y Since the production of clockand step signals by the timer are then resumed, the stepping action willremove one or both of the inputs to B and E, so that it is unnecesaryfor the Go-ahead signal to persist longer. However, if it is desired toinhibit the action of the Wait unit until a step sequence has repeatedseveral times, the D.C. Goahead may be maintained for the desired lengthof time and removed when it is desired to introduce the Wait action atthe next occurrence of the step number supplied to the unit.

The A.C. Go-ahead is supplied through input D to Q28 which functions asa pulse generator similar to the Q2 stage of the Timer (FIG. 3).Normally input D is negative or an open circuit. The base of Q28 isnegative due to the connection through resistor 1% to -V, and Q28 isconducting. This applies ground potential from its collector to the baseof Q39, allowing Q39 to produce an inhibiting signal if the inputs S, Eand B are at ground. However, if ground potential is applied to input D,a positive transient is applied through capacitor 108 to the base ofQ23, turning that transistor oit and applying a negative potential tothe base of Q30. This turns Q30 on, thus removing the inhibiting signalat output C.

The duration of the interval during which Q28 keeps Q3@ on is determinedby the time constant of the discharge of capacitor MES, and is madesuiiiciently long to allow the timer to generate at least the next stepsignal so as to remove the preceding step signals at inputs B and E. Y

Before another A.C. Go-ahead signal can be effective, capacitor lltimust be allowed to charge, This may be accomplished by opening the inputcircuit to D, or bringing D to a negative potential. This is indicatedin FIG. 8b, where 169 indicates a minimum interval during which anegative signal should be applied (or the input to D broken) before anew go-ahead can be effected at 11G.

it will be appreciated from the foregoing description of FTGS. l and 2,and the description of the specific modular units, that the units can beinterconnected to give many diterent sequences to fit a wide variety ofcontrol applications. FGS. 9 and l0 give two more examples.

Referring to FTG. 9, this system was designed to control the recordingof digits from a computer. Three series of six digits each were to berecorded by a typewriter. The computer contained ya shift registercapable of receiving six digits and shifting them in sequence to providea digital output in sequence to be recorded. Overall, it was required togate pulses corresponding to the first six digits into the shiftregister, record each digit in succession and shift the register betweendigits, and then repeat the operation for the next G-digit number andagain for the third 6-digit number. The typewriter was to be tabbed todifferent positions for different 6-digit numbers, and eventually thecarriage returned to its initial position ready for another cycle.

The operation is initiated by a foot switch, and step 0 is simply a Waitwith a Go-ahead signal obtained from a foot switch, as indicated. Whenthe Go-ahead signal is produced, the system proceeds to step l, and thestep 1 output is used to gate information into the register, asindicated. At step 2 the rst digit is recorded. At step 3 the registeris shifted so as to produce an output corresponding to the second digit.To record the second digit, a Jump unit is actuated by step 3, asindicated, and

the system goes back to step 2, as indicated by line 111, so as torecord the second digit.

The sequence of steps 2 and 3 is repeated until the repeat counter I112has counted the necessary number of times, whereupon the .countersupplies an inhibiting signal through line 1111-3 to the Jump unit. Thisallows steppingy to step 4. The step 4 output is supplied to a Jump unitas indicated, but the jump action is normally inhibited by a signal inline 114. Thus, when step 4 is reached the first time, operationproceeds in normal stepping sequence tostep 5, as indicated by line 115.The output at step 5 is used to tab the recorder carriage.

At step 6, the register is shifted to yield an output corresponding tothe first digit in the second 6-digit number. Since the tabbing kof thecarriage takes more time than the operation of the shift register, adelay 116 is introduced yat step v6. A jump H7 is also introduced atstep 16 so that, after the delay, `oper-ation jumps back to step 2, andsteps 2 and 3 are repeated as described above so as to record the secondseries of six digits.

In this particular operation it is desired for jump 117 to take placeafter each occurrence of step 6, so that an unconditional jump suicies.This is obtained by applying a negative voltage through line T18 to theinhibit input B thereof, so that the jump is never inhibited.

After typing out the second 6-digit series, another tab operation isproduced at step 5. The action is then repeated for the third 6digitseries. Counter 119 counts the number of tab 1operations and after ltwooperations its normal inhibiting output in line 1:14 is removed, therebyallowing the jump at step 4 to take place after the recording of thethird 6-digit group has taken place. At this time the jump unit sets thestepper to step 7, as indicated by line 121. At step 7, the typewritercarriage l2 is returned to its initial condition. A certain amount oftime is required for this to take place, and accordingly a delay isintroduced at step 8, as indicated.

This completes the desired control sequence and the system is ready tobe returned to its O-step condition. This could be accomplished byincorporating a jump at step 8 to jump back to 0. However, since a 9thstep is available (with two stepper units in tandem), the sysytem isstepped quickly through step 9 and back to step 0, as indicated by line122. The system is then in readiness to repeat thc operation on the nextclosure of the foot switch.

The manner in which the units are interconnected to give the actiondescribed in FIG. 9 wiil be clear from the example of FIGS. l and 2.

PEG. l0 shows a control system for a somewhat similar purpose, but inwhich the control Ysequence differs materiaiiy. Here it was desiredV topunch cards in accordance wtih the output of a computer. The computercontained an accumulator which accumulated the pulse data, and the datawas transferred to a buffer for recording. The Output of the buffer wasdecoded andthe cards punched in accordance with the decoded information.

This control unit also is .designed to be -put into opera-tion uponreceipt of a go-ahead signal. Accordingly, step O includes a Wait unit.Upon receipt of the go-ahead signal, step l takes place and the outputat step i is used to close a gate No. ji which blocks further supply ofdata pulses to the accumulator. At step 2, a gate No. 2 is opened totransfer the pulse data from the accumulator to the buffer. At step 3the accumulator is cleared, ready to receive new data. At step 4, gateNo. 1 is opened to allow the accumulator to accumulate new data, anddecoding of thefbuffer information begins.

.The decoding involved the actuation rof relays, and accordingly a delay123 is introduced at step 4'. The systern then steps through decodingstep 5 to step 6, where a punch is actuatedr in accordance with thedecoded information. Rather than introducing the relay at step 4 ytoprovide time for decoding,` it could be introduced at step 5 instead.The punching operation also required a time greater than the stepinterval, so delay 124 is introduced at step 6. At the end of thisdelay, operation proceeds to step 7 where the punch is released. Thisrequired some delay also, and delay'lZS is introduced.

At step 8, the buffer is shifted one bit, and the system is ready fordeconding the second bit. Consequently, a jump T26 is introduced to jumpback to step 4, as indicated by line 127. A counter 128 counts theVnumber of jumps, and after the required number (13 in this case)supplies an inhibiting signal through line 129 to jump 126, therebyallowing operation to proceed to step 9. At this step the outputactuated a card release and a card counter. This took a time greaterthan the step interval so a delay T311 is introduced. After this delay,`opera-tion returns to step O, ready for the next go-ahead signal.

VThe invention has been described in connection with specificembodiments of the modular control units, and several examples ofspecific combinations of the control units 'to effect particular`control sequenceshave been given to illustrate the usefulness thereof.kWhile the specific control units described have features which arebelieved to be particularly advantageous, it wil-l be understood thatthey may be modiiiied or elaborated as meets the requirements of theintended applications.

I claim:

i. A modular electronic control circuit which comprises a timer moduleincluding means for producing a series of spaced stepper pulses, astepper module having a plurality of step stages for producing controlsignal outputs at the corresponding steps and means for stepping fromone stage to the next successively in sequence in response to successivestepper pulses applied thereto from the timer module, said steppermodule including means Vfor individually setting the` stages todifferent steps in i3 4 response to corresponding step set signals, ajump module including means for producing a step set signal output inresponse to a selectable control signal output from the stepper modulemeans and means for inhibiting the production of the step set signaloutput in response to a jump inhibiting signal, and connections betweensaid timer, stepper and jump modules for producing stepping and jumpaction-s in a desired sequence.

2. A modular electronic control circuit which comprises a timer moduleincluding means for producing a series of spaced stepper pulses andmeans for inhibiting the production of the stepper pulses in response totimer inhibiting signals applied thereto, a stepper module having aplurality of step stages for producing control signal outputs at thecorresponding steps and means for stepping from one stage to the nextsuccessively in sequence in response lto successive stepper pulsesapplied thereto from the timer module, said stepper module includingmeans for individually setting the stages to different steps in responseto corresponding step set signals, a jump module including means forproducing a step set signal output in response to a selectable controlsignal output from the stepper module and means for inhibiting theproduction of the step set signal output in response to a jumpinhibiting signal, and connections between said timer, stepper and jumpmodules for producing stepping and jump actions in a desired sequence.

3. A modular electronic control circuit in accordance with claim 2including a delay module including means for producing a timerinhibiting signal in response to a selectable control signal output fromthe stepper module, and connections between the delay module and thetimer `and stepped modules for introducing a delay at a desired step.

4. A modular electronic control circuit in accordance with claim 2including a wait module including means `for producing a timerinhibiting sign-al in 4response to a selectable control signal outputfrom the stepper module .and means for terminating the timer inhibitingsignal in response to a go-ahead signal applied thereto, and connectionsbetween the wait module and the timer and stepper modules for producinga Wait action at a desired step.

5. A modular electronic control circuit in accordance with claim 2 inwhich said timer module includes means for producing a series of clockpulses timed to occur between the stepper pulses and means forinhibiting the production of the clock pulses in response to said timerinhibiting signals, and in which said jump module includes means forinhibiting the production of a step set signal output in the absence ofa clock pulse, and a connection for supplying the clock pulses from thetimer to the jump module.

6. A modular electronic control circuit in accordance with claim 5 whichincludes a delay module including means for producing a timer inhibitingsignal in response to the simultaneous occurrence of a selectablecontrol signal output from the stepper module and a clock pulse from thetimer module, connections from the timer and stepper modules to thedelay module for supplying thereto clock pulses and a control signal ata desired step, and a connection from the delay to the timer module forsupplying 4a timer inhibiting signal thereto.

7. A modular electronic control circuit in accordance with claim 5including a Wait module including means for producing a timer inhibitingsignal in response to the simultaneous occurrence of a selectablecontrol signal output from the stepper module and a clock pulse from thetimer module, the wait module including means for receiving a go-aheadsignal `and means responsive thereto for terminating the timerinhibiting signal, connections from the timer and stepper modules to thewait module for supplying thereto clock pulses and a control signal at adesired step, and a connection from the wait to the timer modules forsupplying a timer inhibiting signal thereto.

8. A modular electronic control circuit which comprises a timer moduleincluding means for producing a series of spaced stepper pulses and aseries of clock pulses timed to occur between the stepper pulses, meansfor inhibiting the production of the stepper and clock pulse signals inresponse to timer inhibiting signals applied thereto, and a single-steppulse generator responsive to a corresponding input signal foroverriding the inhibiting means and allow the production of a singlepair of stepper and clock pulses; a stepper module having a plurality ofbistable multivibrator step stages each producing a control signaloutput at the corresponding step in one of the bistable states thereof,means for actuating the stages to said one state successively insequence in response to successive stepper pulses applied thereto, meansfor clearing the stages to the other state thereof in response to anapplied step clear signal, and means for indiwidually setting any stageto said one state in response to a corresponding applied step setsignal; a jump module including input circuits for receiving aselectable control signal output from the stepper module and the clockpulse signal from the timer module, means for producing step clear andstep set signals in response to the simultaneous occurrence of controland clock pulse signals at the inputs thereof, the step clear and stepset signals being produced upon the termination of the clock pulse, andmeans for inhibiting the production of the step clear and step setsignals in response to -a jump inhibiting signal applied thereto; andconnections for supplying stepper pulses from timer to stepper modules,clock pulse signal from timer to jump modules, a control signal from astep of the stepper moduler to the jump module, the step clear signalfrom the jump to stepper modules and the step set signal to a stagethereof, said connections producing stepping and jump actions in adesired sequence.

9. A modular electronic control circuit in accordance with claim 8including a delay module including input circuits for receiving aselectable control signal output from the stepper module and the clockpulse signal from the timer module, and means for producing a timerinhibiting signal in response to the simultaneous occurence of controland clock pulse signals at the inputs thereof; `and connections forsupplying the clock pulse signal from timer to delay modules, a controlsignal from a step of the stepper module to the delay module, and thetimer inhibiting signal from delay to timer modules, said connectionsintroducing a delay at a desired step.

10. A modular electronic control circuit in accordance with claim 9including a wait module including input circuits for receiving a controlsignal from the stepper module and the clock pulse signal from the timermodule, means for producing a timer inhibiting signal in response to thesimultaneous occurrence of control and clock pulse signals at the inputsthereof, an input circuit for receiving a go-ahead signal, and meansresponsive to a received go-ahead signal for terminating the timerinhibiting signal; and connections for supplying the clock pulse signalfrom timer to wait modules, a control signal from a step of the steppermodule to the wait module, and the timer inhibiting signal from the Waitto timer modules, said connections introducing a wait at a desired stepwhich is terminable by a g-o-ahead signal to the Wait module.

11. A timer module for a modular electronic control circuit whichcomprises an oscillator, pulse generating means for receiving theoscillator output and generating a series of spaced stepper pulses insynchronism therewith and a series of clock pulses timed to occurbetween the step pulses, Ioutput terminals supplied with said stepperand clock pulses respectively, a plurality of input circuits forreceiving timer inhibiting signals, and inhibiting means responsive toan inhibiting signal in any of said input circuits for inhibiting saidoscillator.

12. A timer module in accordance with claim 11 including an inputcircuit for receiving `a single-step input signal, a pulse generator forgenerating a pulse in response

1. A MODULAR ELECTRONIC CONTROL CIRCUIT WHICH COMPRISES A TIMER MODULEINCLUDING MEANS FOR PRODUCING A SERIES OF SPACED STEPPER PULSES, ASTEPPER MODULE HAVING A PLURALITY OF STEP STAGES FOR PRODUCING CONTROLSIGNAL OUTPUTS AT THE CORRESPONDING STEPS AND MEANS FOR STEPPING FROMONE STAGE TO THE NEXT SUCCESSIVELY IN SEQUENCE IN RESPONSE TO SUCCESSIVESTEPPER PULSES APPLIED THERETO FROM THE TIMER MODULE, SAID STEPPERMODULE INCLUDING MEANS FOR INDIVIDUALLY SETTING THE STAGES TO DIFFERENTSTEPS IN RESPONSE TO CORRESPONDING STEP SET SIGNALS, A JUMP MODULEINCLUDING MEANS FOR PRODUCING A STEP SET SIGNAL OUTPUT IN RESPONSE TO ASELECTABLE CONTROL SIGNAL OUTPUT FROM THE STEPPER MODULE MEANS AND MEANSFOR INHIBITING THE PRODUCTION OF THE STEP SET SIGNAL OUTPUT IN RESPONSETO A JUMP INHIBITING SIGNAL, AND CONNECTIONS BETWEEN SAID TIMER, STEPPERAND JUMP MODULES FOR PRODUCING STEPPING AND JUMP ACTIONS IN A DESIREDSEQUENCE.